A cikin fagagen kuɗin dijital, blockchain, da ɓoyayyen bayanai na gajimare, hanyoyin ɓoyewa da buɗewa na gargajiya na software suna fuskantar ƙalubale masu mahimmanci da suka haɗa da jinkirin lissafi, yawan amfani da albarkatun mai masaukin baki, da buƙatun wutar lantarki masu yawa. Yayin da aiwar Field Programmable Gate Array (FPGA) ta amfani da Verilog/VHDL ke ba da ƙarfafa kayan aiki, suna fama da tsawaita zagayowar ci gaba da wahalar kulawa da haɓakawa. Wannan takarda tana magance waɗannan iyakoki ta hanyar gabatar da sabon zane na na'urar ƙarfafa FPGA don algorithm 3DES ta amfani da tsarin OpenCL.
Zanen da aka gabatar yana aiwatar da tsarin aiki tare da layin ruwa mai maimaitawa 48. Dabaru na ingantawa sun haɗa da daidaita ajiyar bayanai da inganta faɗin bit na bayanai a cikin na'urar watsa bayanai don haɓaka amfani da bandwidth na tsakiya, tare da inganta kwararar umarni a cikin na'urar ɓoyayyen bayanai ta algorithm don samar da ingantaccen tsarin aiki tare da layin ruwa. Ana samun ƙarin ribar aiki ta hanyar vectorization na tsakiya da kwafin na'urar lissafi.
Matsakaicin Gudanarwa akan Intel Stratix 10 GX2800
Ribar aiki idan aka kwatanta da Intel Core i7-9700 CPU
Ribar ingancin makamashi idan aka kwatanta da CPU
Ribar Aiki & Ingantawa idan aka kwatanta da NVIDIA GTX 1080 Ti GPU
Algorithm ɗin Ma'aunin ɓoyayyen Bayanai sau Uku (3DES) an gina shi akan algorithm ɗin DES, yana haɓaka tsaro ta hanyar ayyukan DES guda uku a jere. Yayin da DES ke amfani da maɓalli mai bit 56 da maimaitawa 16, 3DES yana amfani da maɓalli mai bit 168 da maimaitawa 48.
Algorithm ɗin DES yana aiki akan tubalan bayanai na bit 64. Babban aikinsa, cibiyar sadarwar Feistel, ana iya wakilta shi kamar haka: $L_i = R_{i-1}$ $R_i = L_{i-1} \oplus F(R_{i-1}, K_i)$ Inda $L_i$ da $R_i$ suke rabin hagu da dama na tubalin bayanai a zagaye $i$, $K_i$ shine maɓallin zagaye, kuma $F$ shine aikin zagaye wanda ya haɗa da faɗaɗawa, musanya S-box, da jujjuyawa.
3DES yana amfani da DES sau uku tare da ko dai maɓallai biyu masu zaman kansu ko uku (yanayin EDE): $Ciphertext = E_{K3}(D_{K2}(E_{K1}(Plaintext)))$. Wannan tsarin yana ƙara juriya ga hare-haren ƙarfi sosai idan aka kwatanta da DES guda ɗaya.
Na'urar ƙarfafa tana amfani da ƙirar lissafi daban-daban ta OpenCL, yana ba da damar shirye-shiryen tsakiya su kasance a haɗe kuma a aiwatar da su akan na'urorin FPGA. Wannan hanya tana haɗa gibin tsakanin sassaucin software da aikin kayan aiki.
Tsarin ya ƙunshi mai masaukin baki (CPU) wanda ke sarrafa kwararar sarrafawa da canja wurin bayanai, da na'ura (FPGA) wanda ke aiwatar da tsakiya mai nauyin lissafi na 3DES. An tsara tsakin FPGA tare da tsari mai zurfi na layin ruwa don sarrafa tubalan bayanai da yawa a lokaci guda.
Tsarin zanen shine layin ruwa mai mataki 48 wanda yayi daidai da maimaitawa 48 na 3DES. Kowane mataki an daidaita shi a hankali don tabbatar da babban mitar agogo da cikakken amfani da layin ruwa, yana ɓoye jinkirin ayyuka ɗaya.
Wannan na'ura tana sarrafa motsin bayanai tsakanin ƙwaƙwalwar mai masaukin baki da babban ƙwaƙwalwar ajiya ta FPGA. Ana amfani da dabaru kamar canja wuri mai fashewa da samun damar ƙwaƙwalwar ajiya daidai don cimma kusan madaidaicin bandwidth na ka'idar. Amfani da mafi faɗin hanyoyin sadarwa na AXI (misali, bit 512) shine babban abu mai mahimmanci wajen inganta ingantaccen bandwidth.
Wannan na'ura tana aiwatar da zagayowar Feistel na 3DES. S-boxes, waɗanda a al'ada ana aiwatar da su azaman teburin nema (LUTs), an inganta su don abubuwan dabaru na FPGA. Aikin jujjuyawa da faɗaɗawa an haɗa su cikin hanyar bayanai.
Ana iya ƙirar jimillar gudanarwa $T$ na na'urar ƙarfafa kamar haka: $T = f_{clk} \times W \times N_{CU} \times \eta$ Inda $f_{clk}$ shine mitar aiki, $W$ shine faɗin bit ɗin da aka sarrafa kowace zagaye, $N_{CU}$ shine adadin na'urorin lissafi, kuma $\eta$ shine ma'aunin ingancin layin ruwa (kusa da 1 don ingantaccen zane).
An aiwatar da na'urar ƙarfafa akan FPGA na Intel Stratix 10 GX2800. Sakamakon farko shine:
vs. CPU (Intel Core i7-9700): Na'urar ƙarfafa FPGA tana nuna haɓakar aiki mai 372x da haɓaka mai ban mamaki na 644x a ingancin makamashi (Aiki/Watt). Wannan yana nuna fifikon FPGA don ƙayyadaddun tsakiya, masu nauyin lissafi.
vs. GPU (NVIDIA GeForce GTX 1080 Ti): FPGA ya cimma mafi girma gudanarwa da 20% da ingantaccen ingancin makamashi mai 9x. Yayin da GPU suka yi fice a babban aiki tare akan bayanai na yau da kullun, FPGA na iya cimma mafi girman inganci akan ayyukan bit-level da layin ruwa na al'ada, kamar yadda aka gani a cikin algorithms na ɓoyayyen bayanai.
Zanen yana amfani da albarkatun FPGA yadda ya kamata. Ma'auni masu mahimmanci sun haɗa da:
Tsarin don Kimanta Na'urorin Ƙarfafa Crypto na Kayan Aiki:
Nazarin Lamari - Ƙofar ɓoyayyen Bayanai na Gajimare: Ka yi tunanin sabis na ajiyar gajimare mai tsaro wanda ke ɓoye duk bayanai a hutu ta amfani da 3DES. Maganin software kawai akan uwar garken Xeon na iya zama cikas. Ta hanyar ƙaddamar da ɓoyayyen bayanai na 3DES zuwa katin ƙarfafa FPGA (kamar Intel PAC tare da Stratix 10), sabis ɗin zai iya samun mafi girman jimillar gudanarwa, ƙarancin jinkiri don buƙatun ɗaya saboda layin ruwa na kayan aiki, da rage amfani da wutar lantarki na uwar garken da nauyin CPU, yana 'yantar da albarkatu don wasu ayyuka.
Wannan takarda ba kawai game da sa 3DES ya yi sauri ba; tsari ne na dabarun dawo da inganci a cikin zamanin bayan Dokar Moore. Yayin da masana'antu suka kasance cikin ruɗi da ɗanyen FLOPs na GPU don ƙarfafawa, marubutan sun ba da tunatarwa mai ƙarfi: don takamaiman, ƙayyadaddun tsakiya kamar abubuwan farko na ɓoyayyen bayanai, ƙayyadaddun, programmability na bit-level na FPGA na iya ƙetare gabaɗayan manufa, masu cin wutar lantarki na CPUs da GPUs. Ribar ingancin makamashi mai 644x akan CPU na zamani ba haɓaka ce ba—canjin tsari ne ga masu sarrafa cibiyoyin bayanai inda wutar lantarki ke zama cibiyar farashi ta ƙarshe. Wannan aikin ya yi daidai da babban yanayin da aka lura a cikin manyan masu amfani kamar Microsoft da Amazon, waɗanda ke tura FPGA (kuma yanzu ASICs) a ma'auni don ayyuka kamar virtualization na cibiyar sadarwa da canza bidiyo, suna ba da fifikon aiki-kowace-watt akan madaidaicin ka'idar gudanarwa.
Hankalin marubutan yana da gamsarwa kuma yana bin tsari. Sun gano matsala biyu daidai: software yana da jinkiri da rashin inganci, yayin da ci gaban FPGA na gargajiya na HDL yana da jinkiri da tauri. Maganinsu, ta amfani da OpenCL azaman kayan aiki na Haɗin Babban Mataki (HLS), yana magance duka bangarorin biyu cikin kyakkyawa. Dabaru na ingantawa suna bin tsari mai bayyana: na farko, tabbatar da cewa bayanai za su iya gudana zuwa na'urorin lissafi yadda ya kamata (ajiyar bayanai, faɗin bit). Na biyu, tabbatar da cewa na'urorin lissafi da kansu ana amfani da su sosai (inganta umarni, layin ruwa). A ƙarshe, sikelin waje (vectorization, kwafi). Wannan yana kama da tsarin ingantawa don tsakin GPU amma ana amfani da shi akan masana'antar inda "tsakiya" aka gina su na musamman don ainihin aikin. Kwatanta da GTX 1080 Ti yana da faɗi musamman—yana nuna cewa ko da a kan na'urar sarrafawa mai aiki tare, hanyar bayanai na al'ada akan FPGA na iya yin nasara akan duka aiki da, yanke shawara, inganci.
Ƙarfi: Sakamakon aiki da inganci suna da ban mamaki kuma an ƙididdige su sosai. Amfani da OpenCL yana ba da damar masu haɓakawa da mahimmanci da kiyaye gaba, kamar yadda aka lura a cikin ƙayyadaddun OpenCL na Khronos waɗanda ke ba da damar ɗaukar kaya a cikin masu siyarwa. Mayar da hankali kan 3DES, wanda ya rage amma har yanzu ana tura shi da yawa (misali, a cikin tsarin kuɗi), yana magance ainihin buƙatar zamani maimakon aikin ilimi kawai.
Kurakurai & Gibin Mai Muhimmanci: Achilles ɗin takardar shine ƙuntataccen iyakokinta. Ana fitar da 3DES don goyon bayan AES-256 don sabbin tsarin, kamar yadda jagororin NIST suka nuna. Aikin zai fi tasiri idan ya nuna saurin hanyar OpenCL ta hanyar kuma aiwatar da AES ko ɗan takarar bayan quantum, yana nuna ƙimar tsarin fiye da algorithm ɗaya. Bugu da ƙari, binciken ya rasa tattaunawa kan raunin gefen hanya. Aiwa na kayan aiki, musamman wanda ke nufin babban gudanarwa, na iya zama mai saukin kamuwa da hare-haren lokaci ko binciken wutar lantarki. Yin watsi da wannan matakin tsaro babban kuskure ne ga takarda ta ɓoyayyen bayanai. Aikin masu bincike kamar Mangard et al. akan juriya na gefen hanya na kayan aiki shine mahimmancin mahallin da ya ɓace a nan.
Ga Manajoji na Samfura a cikin kamfanonin gajimare ko na'urorin tsaro: Wannan binciken shine tabbacin ra'ayi don tura katunan ƙarfafa na tushen FPGA don ƙaddamar da ayyukan ɓoyayyen bayanai (ƙarewar TLS, ɓoyayyen ajiya). Ceton makamashi kawai ya ba da hujjar aikin gwaji. Ga Masu Zane na Tsaro: Tura masu siyar da ku. Bukatar cewa na'urorin ƙarfafa kayan aiki, ko FPGA ko ASIC, sun haɗa da ƙira masu jure wa gefen hanya a matsayin daidaitaccen fasali, ba bayan tunani ba. Ga Masu Bincike & Masu Haɓakawa: Kada ku tsaya a 3DES. Yi amfani da wannan hanyar OpenCL azaman tushe. Mataki na gaba mai mahimmanci shine gina ɗakin karatu na buɗaɗɗen tushe, ingantaccen, kuma mai jure wa gefen hanya na tsakin OpenCL don jerin algorithms (AES-GCM, ChaCha20-Poly1305, SHA-3, Kyber, Dilithium). Al'umma suna buƙatar ɗaukar kaya, ingantacciya, da tsattsauran gine-gine, ba kawai nunin ɗaya ba. Girman kayan aikin da Intel's oneAPI da Xilinx Vitis suka haskaka a ƙarshe suna sa wannan ya yiwu. Gasar ba kawai don sauri ba ce; don tsaro, inganci, da ƙarfafawa mai daidaitawa.