Na'urar FPGA Mai Haɓaka Algorithm 3DES Dangane da OpenCL

Teburin Abubuwan Ciki

1. Gabatarwa

A fagen kuɗin dijital, blockchain, da ɓoyayyen bayanai na gajimare, hanyoyin ɓoyayye da buɗe bayanai na gargajiya na software suna fuskantar ƙalubale masu yawa da suka haɗa da jinkirin ƙididdiga, yawan amfani da albarkatun kwamfuta, da kuma amfani da wutar lantarki mai yawa. Duk da yake aiwatar da FPGA ta amfani da Verilog/VHDL suna ba da haɓaka kayan aiki, suna fama da tsawon lokacin haɓakawa da wahalar kula da su.

Wannan bincike ya gabatar da wata ƙirar mai haɓaka FPGA mai ƙima dangane da OpenCL don algorithm ɗin 3DES wanda ke magance waɗannan iyakoki ta hanyar ingantattun dabarun inganta aiki da suka haɗa da tsarin aiki tare da juna, daidaita adana bayanai, inganta faɗin bit, inganta magudanar umarni, sassaukar kernel, da kuma kwafin na'urar lissafi.

2. Ka'idojin Algorithm ɗin 3DES

2.1 Algorithm ɗin DES

Algorithm ɗin DES (Ma'aunin ɓoyayyen Bayanai) yana aiki akan tubalan 64-bit ta amfani da maɓalli na 56-bit ta hanyar zagaye 16 na ayyukan cibiyar sadarwar Feistel. Babban aikin lissafi ana iya wakilta shi kamar haka:

$L_i = R_{i-1}$

$R_i = L_{i-1} \oplus f(R_{i-1}, K_i)$

Inda $L_i$ da $R_i$ ke wakiltar rabin hagu da dama na tubalin bayanai, $K_i$ shine maɓallin zagaye, kuma $f$ shine aikin Feistel wanda ya haɗa da faɗaɗawa, haɗa maɓalli, musanya, da ayyuka na musanya.

2.2 Tsarin Algorithm ɗin 3DES

3DES yana haɓaka tsaro ta hanyar amfani da DES sau uku tare da ko dai maɓalli biyu ko uku daban-daban. Tsarin ɓoyayye yana biye da:

$C = E_{K3}(D_{K2}(E_{K1}(P)))$

Inda $E$ ke wakiltar ɓoyayye, $D$ ke wakiltar buɗewa, $P$ shine bayanan fili, $C$ shine bayanan sirri, kuma $K1$, $K2$, $K3$ su ne maɓallan 56-bit guda uku. Wannan tsarin yana ba da zagaye 48 na ɓoyayye tare da tsayin maɓalli mai inganci na 168-bit.

3. Ƙirar Mai Haɓaka FPGA Dangane da OpenCL

3.1 Bayyani Gabaɗaya na Tsarin Gina

Mai haɓaka da aka gabatar yana amfani da cikakken tsarin aiki tare da juna tare da maimaitawa 48 da aka ƙera musamman don algorithm ɗin 3DES. Tsarin ginin ya ƙunshi manyan na'urori guda biyu: na'urar watsa bayanai da na'urar ɓoyayyen algorithm, waɗanda aka inganta don matsakaicin ɗorawar kaya akan FPGA ɗin Intel Stratix 10 GX2800.

3.2 Inganta Watsa Bayanai

Na'urar watsa bayanai tana aiwatar da muhimman dabaru guda biyu:

• Daidaita Ajiyar Bayanai: Yana inganta hanyoyin samun ƙwaƙwalwar ajiya don rage jinkiri
• Inganta Faɗin Bit na Bayanai: Yana ƙara faɗin hanyar bayanai don haɓaka amfani da bandeji

Waɗannan ingantattun suna cimma sama da kashi 85% na amfani da bandeji na ainihin kernel, wanda ya fi girma sosai fiye da aiwatarwa na al'ada.

3.3 Na'urar ɓoyayyen Algorithm

Na'urar ɓoyayye tana amfani da inganta magudanar umarni don ƙirƙirar tsarin aiki tare da juna mai zurfi. Muhimman fasaloli sun haɗa da:

• Mataki 48 na bututun ruwa don zagayen 3DES
• Tsara maɓalli tare da juna
• Ingantattun aiwatar da akwatunan S
• Rage dogaro da bayanai tsakanin zagayawa

3.4 Dabarun Haɓaka Aiki

Ana samun ƙarin haɓaka aiki ta hanyar:

• Sassaukar Kernel: Amfani da ayyukan SIMD don sarrafa bayanai tare da juna
• Kwafin Na'urar Lissafi: Na'urori masu yawa na lissafi tare da juna don ƙara ɗorawar kaya
• Inganta Samun Ƙwaƙwalwar Ajiya: Haɗa samun ƙwaƙwalwar ajiya da amfani da ƙwaƙwalwar ajiya na gida

4. Sakamakon Gwaji

Ƙimar gwaji ta nuna manyan nasarorin da aka samu:

Aiwatar da FPGA ta cimma ɗorawar kaya na 111.801 Gb/s yayin da take amfani da ƙarancin wutar lantarki fiye da na CPU da GPU, yana nuna mafi girman ingantaccen amfani da makamashi don aikace-aikacen ɓoyayye.

5. Binciken Fasaha

Binciken Ƙwararru: Ƙima Mai Muhimmanci Ta Matakai Hudu

Yanke zuwa Ga Aikin (Cutting to the Chase)

Wannan bincike yana kawo cikakken gaskiya ga aiwatarwa na ɓoyayye na gargajiya. Haɓaka aikin 372x akan CPU na zamani ba kawai ƙari ba ne—yana rushe tsarin gini. Marubutan a zahiri sun nuna cewa don ayyukan 3DES, na'urori masu sarrafa bayanai na gabaɗaya ba su da inganci, kuma ko da GPU ba za su iya yin daidai da ingantaccen amfani da makamashi na FPGA don wannan takamaiman aikin ba.

Sarkar Hankali (Logical Chain)

Ƙwararren nasara yana biye da tsayayyen matsayi na inganta aiki: Na farko, sun kai hari ga amfani da bandeji na ƙwaƙwalwar ajiya ta hanyar daidaita ajiyar bayanai (sun magance matsalar bangon ƙwaƙwalwar ajiya). Na biyu, sun aiwatar da bututun ruwa mai zurfi don amfani da tsarin 3DES mai zagaye 48. Na uku, sun yi amfani da sassaukarwa da kwafin na'urar lissafi don haɓaka sarrafa bayanai tare da juna. Wannan tsari na tsari yayi kama da dabarun inganta aikin da ake gani a cikin wallafe-wallafen kwamfuta masu ƙarfi, musamman ma binciken Samfurin Roofline da ake amfani da shi a cikin aikin ASPIRE na Berkeley.

Abubuwan Haske da Iyakoki (Highlights and Limitations)

Abubuwan Haske: Haɓaka ingantaccen amfani da makamashi na 644x yana da ban mamaki kuma yana da tasiri na gaske ga ayyukan cibiyar bayanai. Amfani da OpenCL maimakon HDL na gargajiya yana sa wannan hanyar ta zama mai sauƙi ga injiniyoyin software. Kwatanta da CPU da GPU yana ba da cikakken ma'auni.

Iyakoki: Takardar ta mayar da hankali ne kawai akan 3DES, wanda ake cirewa don fifita AES a yawancin aikace-aikace. Akwai ƙaramin tattaunawa game da haɓakawa zuwa wasu algorithms. Intel Stratix 10 GX2800 babban FPGA ne mai ƙima, yana sa ingancin kuɗi don ƙananan turawa ya zama abin tambaya.

Abubuwan Koyo na Aiki (Actionable Insights)

Ga masu samar da gajimare da cibiyoyin kuɗi waɗanda har yanzu suke amfani da 3DES, wannan bincike yana ba da hanyar ƙaura bayyananna zuwa haɓaka FPGA. Hanyar OpenCL tana rage matsalar shiga idan aka kwatanta da haɓaka FPGA na gargajiya. Ƙungiyoyi yakamata su yi la'akari da haɓaka ɓoyayye na tushen FPGA don sarrafa ma'amaloli masu yawa kuma suyi la'akari da wannan tsarin ginin a matsayin samfuri don haɓaka wasu algorithms na ɓoyayye na ma'auni.

Bincike na Asali (kalmomi 400)

Wannan bincike yana wakiltar ci gaba mai muhimmanci a cikin haɓaka ɓoyayye wanda ke haɗa tazara tsakanin samun damar software da aikin kayan aiki. Hanyar marubutan na amfani da OpenCL don haɓaka FPGA tana magance wata muhimmiyar matsala a cikin ƙididdigar ƙididdiga mai ƙarfi: shingen ƙwarewa don haɓaka kayan aiki. Kamar yadda aka lura a cikin ƙayyadaddun OpenCL na Ƙungiyar Khronos, wannan tsarin yana ba da damar "shirye-shiryen tare da juna na tsarin daban-daban ta amfani da ma'auni mai ɗaukar hoto, buɗaɗɗen ma'auni," yana sa ƙididdigar haɓaka ta zama mai sauƙi ga masu haɓakawa na yau da kullun.

Ɗorawar kaya na 111.8 Gb/s da aka samu yana nuna tasirin tsarin aiki tare da juna don ayyukan ɓoyayye. Wannan aikin ya yi daidai da yanayin da aka gani a wasu gine-ginen yanki na musamman, kamar TPU na Google don hanyoyin sadarwar jijiya ko na'urorin AI na Intel's Habana Labs. Babban hasashe a nan shine cewa algorithms na ɓoyayye, tare da tsarinsu na yau da kullun da ƙayyadaddun yanayin aiwatarwa, sun dace sosai da haɓaka FPGA.

Idan aka kwatanta da hanyoyin tushen HDL na gargajiya da aka rubuta a cikin IEEE Transactions on VLSI Systems, aiwatar da OpenCL yana ba da fa'idodin ingantaccen haɓakawa. Duk da haka, kamar yadda bincike daga ƙungiyar FPGA ta Jami'ar Toronto ya nuna, yawanci akwai hukunci na aiki lokacin amfani da haɓakawa mai girma idan aka kwatanta da RTL da aka inganta da hannu. Gaskiyar cewa wannan aiwatarwa har yanzu tana samun mafi kyawun aiki ga CPU da GPU yana nuna ingantattun dabarun inganta aiki.

Sakamakon ingantaccen amfani da makamashi (haɓaka 644x akan CPU) yana da jan hankali musamman idan aka yi la'akari da mahimmancin dorewar lissafi. Yayin da cibiyoyin bayanai ke fuskantar ƙuntatawa na wutar lantarki, hanyoyin da ke ba da haɓaka aiki mai yawa ga kowace watt za su zama dole. Wannan bincike ya nuna cewa don takamaiman ƙirar lissafi kamar algorithms na ɓoyayye, FPGAs na iya samar da fa'ida mai girma fiye da gine-ginen gabaɗaya.

Duk da haka, mayar da hankali kan 3DES yana tayar da tambayoyi game da dangi na dogon lokaci. Tare da NIST yana ƙin 3DES don yawancin aikace-aikace kuma yana canzawa zuwa AES, dacewar waɗannan takamaiman ingantattun ga ma'auni na ɓoyayye na zamani ya cancanci ƙarin bincike. Duk da haka, yanayin gine-gine da dabarun inganta aiki, suna yiwuwa a canja su zuwa AES da sauran algorithms na ɓoyayye na ma'auni.

6. Aiwatar da Lambar

Misalin Kernel na OpenCL

__kernel void triple_des_encrypt(
    __global const uint8_t *input,
    __global uint8_t *output,
    __constant uint32_t *key_schedule,
    const uint num_blocks)
{
    int gid = get_global_id(0);
    if (gid >= num_blocks) return;
    
    // Loda tubalin 64-bit
    uint64_t block = *((__global uint64_t*)(input + gid * 8));
    
    // ɓoyayyen 3DES: E_K3(D_K2(E_K1(P)))
    block = des_encrypt(block, key_schedule, 0);      // DES na farko tare da K1
    block = des_decrypt(block, key_schedule, 16);     // DES na biyu tare da K2  
    block = des_encrypt(block, key_schedule, 32);     // DES na uku tare da K3
    
    // Ajiye sakamako
    *((__global uint64_t*)(output + gid * 8)) = block;
}

uint64_t des_encrypt(uint64_t block, __constant uint32_t *keys, int key_offset)
{
    // Musanya na farko
    block = initial_permutation(block);
    
    uint32_t left = (uint32_t)(block >> 32);
    uint32_t right = (uint32_t)block;
    
    // Zagaye 16 na Feistel
    #pragma unroll
    for (int i = 0; i < 16; i++) {
        uint32_t temp = right;
        right = left ^ feistel_function(right, keys[key_offset + i]);
        left = temp;
    }
    
    // Musanya na ƙarshe
    return final_permutation(((uint64_t)right << 32) | left);
}

7. Ayyukan Gaba

Hanyar gine-ginen da aka nuna a cikin wannan bincike tana da fa'ida mai faɗi fiye da ɓoyayyen 3DES:

• Blockchain da Kuɗin Dijital: Dandamalin ciniki mai sauri da ayyukan haƙar ma'adinai na iya amfani da irin wannan haɓaka FPGA don ayyukan ɓoyayye.
• Tsaro na 5G: Za a iya daidaita tsarin bututun ruwa don ma'auni na ɓoyayye na 5G a cikin sarrafa tashar tushe.
• Ƙididdiga na Gefen: Ƙananan aiwatarwa na FPGA na iya samar da haɓaka ɓoyayye don na'urorin IoT da sabar gefe.
• ɓoyayyen Bayanai Bayan Quantum: Za a iya amfani da dabarun inganta aiki ga algorithms na ɓoyayyen bayanai na quantum masu tasowa.
• Masu Haɓaka Algorithm Masu Yawa: Aikin gaba zai iya bincika ƙirar FPGA mai daidaitawa da ke goyan bayan algorithms na ɓoyayye da yawa.

Hanyoyin bincike sun haɗa da binciken aikace-aikacen waɗannan fasahohin inganta aiki ga AES-GCM, ChaCha20-Poly1305, da sauran ma'auni na ɓoyayye na zamani, da kuma bincika kayan aikin inganta aiki ta atomatik waɗanda za su iya amfani da irin waɗannan sauye-sauye ga algorithms na ɓoyayye na sabani.

8. Nassoshi

1. K. Group, "The OpenCL Specification," Khronos Group, 2020.
2. Cibiyar Ƙididdiga da Fasaha ta Ƙasa, "Shawara don Algorithm ɗin ɓoyayyen Bayanai Uku (TDEA) Block Cipher," NIST SP 800-67Rev2, 2017.
3. J. Cong et al., "High-Level Synthesis for FPGAs: From Prototyping to Deployment," IEEE Transactions on CAD, 2011.
4. M. Papadonikolakis et al., "Performance Comparison of GPU and FPGA Architectures for Cryptography," SAMOS, 2010.
5. A. M. et al., "FPGA-based Accelerators of Cryptographic Algorithms," IEEE Transactions on Computers, 2013.
6. Intel Corporation, "Intel FPGA SDK for OpenCL Programming Guide," 2020.
7. Xilinx, "SDAccel Development Environment User Guide," 2019.
8. W. Jiang et al., "A Survey of FPGA-Based Cryptographic Computing," ACM Computing Surveys, 2021.