Na'urar Haɓaka FPGA don Algorithm 3DES Dangane da OpenCL: Ƙira da Binciken Ayyuka

1. Gabatarwa & Bayyani

A cikin fannonin kuɗin dijital, blockchain, da ɓoyayyen bayanai na gajimare, buƙatar sarrafa ɓoyayyen bayanai cikin sauri, ƙarancin wutar lantarki yana da mahimmanci. Aiwatar da algorithms kamar 3DES ta hanyar software na gargajiya suna fama da matsalolin aiki masu mahimmanci, yawan amfani da albarkatun CPU, da ƙara amfani da wutar lantarki. Yayin da Field-Programmable Gate Arrays (FPGAs) ke ba da mafita ta haɓaka kayan aiki, haɓakawa ta amfani da ƙananan Harsunan Bayyana Kayan Aiki (HDLs) kamar Verilog/VHDL yana ɗaukar lokaci mai tsawo kuma yana da rikitarwa.

Wannan takarda ta gabatar da sabon ƙira don na'urar haɓaka algorithm 3DES akan FPGA ta amfani da tsarin Open Computing Language (OpenCL). Tsarin da aka gabatar yana amfani da haɓaka matakin girma (HLS) don haɗa gibin samarwa, yana aiwatar da tsarin aiki tare da layi mai maimaitawa 48. Ta hanyar ingantattun dabarun—ciki har da daidaita ajiyar bayanai, inganta faɗin bit, inganta jerin umarni, vectorization na kernel, da kwafin naúrar lissafi—ƙirar ta sami gagarumin nasara a aiki da ingantaccen amfani da makamashi idan aka kwatanta da dandamalin CPU da GPU.

111.8 Gb/s

Matsakaicin Gudanarwa akan Intel Stratix 10

372x

Aiki idan aka kwatanta da Intel Core i7-9700

9x

Ingantaccen Amfani da Makamashi idan aka kwatanta da NVIDIA GTX 1080 Ti

2. Bayanin Fasaha

2.1 Algorithm ɗin 3DES

Ma'aunin ɓoyayyen bayanai sau uku (3DES) maɓalli ne na siminti wanda aka samo daga tsohon algorithm ɗin DES. Don haɓaka tsaro daga hare-haren ƙarfi, 3DES yana amfani da cipher ɗin DES sau uku akan kowane toshe na bayanai. Ma'auni ya ayyana zaɓuɓɓukan maɓalli guda uku, tare da mafi aminci ta amfani da maɓalli uku masu zaman kansu (Zaɓin Maɓalli 1): $C = E_{K3}(D_{K2}(E_{K1}(P)))$, inda $E$ ke nufin ɓoyewa, $D$ ke nufin buɗewa, $K1, K2, K3$ su ne maɓallan, $P$ shine bayanan fili, kuma $C$ shine bayanan ɓoyayye. Wannan yana haifar da ingantaccen tsawon maɓalli na bit 168 da zagaye 48 na lissafi.

2.2 OpenCL don Shirye-shiryen FPGA

OpenCL ma'auni ne buɗaɗɗe, mara biyan kuɗi don shirye-shiryen aiki tare a cikin dandamoli daban-daban (CPUs, GPUs, FPGAs, DSPs). Don FPGAs, kayan aiki kamar Intel FPGA SDK don OpenCL suna aiki azaman mai haɗa kai na Haɓaka Matakin Girma (HLS), suna fassara lambar kernel da aka rubuta a cikin harshe mai kama da C zuwa ingantattun da'irori na kayan aiki. Wannan taƙaitaccen bayani yana rage lokacin haɓakawa da rikitarwa sosai idan aka kwatanta da ƙirar RTL, yana sa haɓakar FPGA ta kasance ga masu haɓaka software da ƙwararrun fanni.

3. Tsarin Na'urar Haɓakawa & Ƙira

3.1 Tsarin Aiki Tare da Layi

Tsakiyar na'urar haɓakawa ita ce tsarin aiki mai zurfi wanda ke buɗe zagaye 48 na algorithm ɗin 3DES. Wannan ƙirar tana ba da damar sarrafa tubalan bayanai da yawa a lokaci guda a matakai daban-daban na layin ɓoyewa, yana haɓaka amfani da kayan aiki da gudanarwa sosai. An daidaita layin aiki da kyau don guje wa tsayawa da tabbatar da ci gaba da kwararar bayanai.

3.2 Ingantaccen Watsa Bayanai

Don shawo kan matsalar ƙarfin ƙwaƙwalwar ajiya da aka saba gani a cikin ƙirar na'urar haɓakawa, ana amfani da manyan dabarun guda biyu:

Daidaita Ajiyar Bayanai: Inganta tsarin bayanai a cikin ƙwaƙwalwar ajiya ta mai gida da na'ura don ba da damar ingantaccen canja wurin fashewa da rage jinkirin samun dama.
Inganta Faɗin Bit na Bayanai: Ƙara faɗin hanyoyin bayanai tsakanin ƙwaƙwalwar ajiya da kernel don dacewa da iyawar bas ɗin ciki na FPGA, ta haka yana inganta ingantaccen amfani da ƙarfin ƙwaƙwalwar ajiya.

3.3 Dabarun Ingantawa na Kernel

Ana inganta kernel ɗin OpenCL ta amfani da dabaru da yawa:

Inganta Jerin Umarni: Sake tsarawa da sauƙaƙe ayyuka don ƙirar ingantaccen jadawalin layin aiki, rage dogaro da zagayowar aiki mara amfani.
Vectorization na Kernel: Yin amfani da ayyukan Single Instruction, Multiple Data (SIMD) don sarrafa abubuwa da yawa na bayanai a lokaci guda a cikin misalin kernel guda ɗaya.
Kwafin Naúrar Lissafi: Ƙirƙirar kwafin da yawa na ingantaccen kernel (Naúrar Lissafi) akan kayan FPGA don sarrafa rafukan bayanai masu zaman kansu a lokaci guda, yana ƙididdige aiki tare da albarkatun da ake da su.

4. Sakamakon Gwaji & Aiki

An aiwatar da na'urar haɓakawa kuma an gwada ta akan Intel Stratix 10 GX2800 FPGA. Ma'auni masu mahimmanci na aiki sune kamar haka:

Gudanarwa: An sami matsakaicin gudanarwa na 111.801 Gb/s.
idan aka kwatanta da CPU (Intel Core i7-9700): Aiki ya inganta da kashi 372, tare da ingantaccen amfani da makamashi 644 sau mafi kyau.
idan aka kwatanta da GPU (NVIDIA GeForce GTX 1080 Ti): Ya fi girma a duka ma'auni, yana ba da aiki mafi girma da kashi 20% da ingantaccen amfani da makamashi sau 9 mafi kyau.

Bayanin Chati (An fayyace): Chati na sandar zai iya nuna wannan kwatancen da kyau. Axis na x zai jera dandamoli uku (Stratix 10 FPGA, Core i7 CPU, GTX 1080 Ti GPU). Za a iya amfani da axis na y biyu: na hagu don Gudanarwa (Gb/s), yana nuna sandar guda ɗaya mai girma sosai don FPGA; na dama don Aiki da aka Daidaita (CPU=1), yana nuna sandar FPGA a 372 da sandar GPU sama da 1 kaɗan. Wani chati na sandar da aka tattara zai iya nuna Ingantaccen Amfani da Makamashi (Ops/J ko makamantansu), yana nuna babban jagorancin FPGA na 644x akan CPU da 9x akan GPU.

5. Fahimtar Tsaki & Ra'ayi na Mai Bincike

Fahimtar Tsaki: Wannan takarda ba kawai game da sa 3DES ya yi sauri akan FPGA ba ne; yana da ƙa'idar ƙira mai ƙarfi don haɓaka haɓakar kayan aiki ga kowa. Marubutan sun nuna cewa ta hanyar amfani da HLS na tushen OpenCL da dabarun dabarun, za ku iya samun aikin da ba wai kawai ya fi na CPUs na gabaɗaya ba har ma ya zarce manyan GPUs a cikin wani yanki da aka yi niyya, duk yayin da ake guje wa tsadar injiniyanci na ƙirar RTL ta gargajiya.

Tsarin Ma'ana: Hujjar tana da tsari. Ta fara ne da gano mahimman matsalolin rauni a cikin software (jinkiri) da haɓakar FPGA na gargajiya (mai wahala). Hanyar mafita a bayyane take: yi amfani da OpenCL/HLS don samarwa, sannan a yi amfani da jerin ingantattun dabarun da aka fahimta amma masu mahimmanci (tsarin layin aiki, vectorization, kwafi) don cire matsakaicin ingancin kayan aiki. Kwatancen aiki da kafofin CPU da GPU da aka kafa suna tabbatar da duk hanyar.

Ƙarfi & Kurakurai: Ƙarfin ba shakku ne: rahotannun ribar 372x/644x akan CPU na zamani suna mamaki kuma suna nuna ainihin yuwuwar kayan aiki na musamman. Amfani da OpenCL babban ƙarfi ne mai amfani, yana daidaitawa da yanayin masana'antu zuwa ingantaccen lissafi daban-daban, kamar yadda aka gani a cikin tsarukan kamar TensorFlow don ML ko OneAPI. Duk da haka, kuskure mai mahimmanci shine rashin kwatancen tushe tare da ingantaccen tsakiyar 3DES na Verilog/VHDL da aka sarrafa da hannu akan FPGA ɗin Stratix 10 ɗaya. Yayin da kwatancen GPU/CPU yana da kyau don sanya kasuwa, al'ummar HLS suna buƙatar sanin "gibin inganci" tsakanin HLS da ƙirar RTL na ƙwararru don wannan takamaiman matsala. Bugu da ƙari, kamar yadda bincike daga Jami'ar Toronto akan samar da HLS ya lura, taƙaitaccen bayani na iya ɓoye sarrafa ƙananan matakai a wani lokaci, yana barin wasu ayyuka akan tebur idan aka kwatanta da ingantaccen aiwatar da RTL.

Fahimta Mai Aiki: Ga ƙungiyoyin samfur, saƙon a bayyane yake: Don ayyukan ɓoyayyen bayanai masu yawa, ayyukan aiki da aka kayyade (fiye da 3DES kawai), na'urar haɓaka FPGA na tushen OpenCL ya kamata ya zama mai fafatawa a lokacin kimanta tsarin gine-gine, musamman inda ingantaccen amfani da wutar lantarki ke da mahimmanci (misali, cibiyoyin bayanai na gefe, na'urorin hanyar sadarwa). Hanyar tana iya canzawa. Ainihin abin da za a ɗauka shine littafin wasan ingantawa—tsarin bayanai, faɗin bit, tsarin layin aiki, vectorization, kwafi. Waɗannan ba sababbin ra'ayoyi ba ne, amma ganin an yi amfani da su tare a cikin mahallin OpenCL don doke babban GPU alama ce mai ƙarfi. Mataki na gaba shine amfani da wannan ƙira ɗaya zuwa algorithms na ɓoyayyen bayanai bayan-quantum kamar Kyber ko Dilithium, waɗanda ke da ƙarfin lissafi kuma manyan 'yan takara ne don irin wannan haɓakawa.

6. Cikakkun Bayanan Fasaha & Tsarin Lissafi

Tsarin ɓoyayyen bayanai na 3DES tare da maɓalli uku masu zaman kansu (yanayin EDE) an ayyana shi a hukumance kamar haka:

$Ciphertext = E_{K_3}(D_{K_2}(E_{K_1}(Plaintext)))$

Inda aikin zagaye na DES guda ɗaya $F(R, K)$, wanda aka yi amfani da shi a kowane zagaye 16 a kowane aikin DES, yana da mahimmanci ga lissafin. Ya ƙunshi:

Faɗaɗawa: An faɗaɗa rabin dama na bit 32 $R$ zuwa bit 48 ta hanyar tebur mai ƙayyadaddun matsayi $E$.
Haɗa Maɓalli: An haɗa faɗaɗaɗɗen $R$ tare da maɓallin zagaye na bit 48 $K$ wanda aka samo daga babban maɓalli.
Maye gurbin (Akwatin-S): An raba sakamakon bit 48 zuwa guntu guda takwas na bit 6, kowannensu an canza shi zuwa fitarwa na bit 4 ta hanyar akwatin maye gurbin mara layi (Akwatin-S). Wannan shine ainihin aikin mara layi: $S(B) = S_i(B)$, inda $B$ shine shigarwar bit 6 kuma $S_i$ shine teburin Akwatin-S na $i^{th}$.
Matsayi (Akwatin-P): An canza fitarwar bit 32 daga Akwatin-S ta hanyar aiki mai ƙayyadaddun $P$.

Fitarwar aikin zagaye ita ce: $F(R, K) = P(S(E(R) \oplus K))$.

Layin aiki na na'urar haɓakawa yana lissafin wannan aikin $F$ sau 48 a kowane toshe na bayanai, tare da matakan layin aiki suna yin taswira zuwa ayyukan faɗaɗawa, XOR, neman Akwatin-S, da ayyukan matsayi, duk an inganta su don aiwatarwa tare.

7. Tsarin Bincike & Misalin Hali

Tsarin don Kimanta Na'urorin Haɓakawa na Tushen HLS:

Lokacin nazarin takarda irin ta wannan, muna amfani da tsarin mai girma da yawa:

Aiki: Matsakaicin gudanarwa (Gb/s) da jinkiri. Kwatanta da kafofin da suka dace (CPU, GPU, wasu ayyukan FPGA).
Inganci: Aiki kowace Watt (Ingantaccen Amfani da Makamashi). Amfani da albarkatu (Abubuwan Lissafi, BRAM, tubalan DSP akan FPGA).
Samarwa: An nuna lokacin haɓakawa da aka ajiye ta amfani da OpenCL idan aka kwatanta da HDL. Canza lambar a cikin iyalan FPGA.
Ingancin Hanyar Aiki: Shin an bayyana dabarun ingantawa da gaskiya? Shin saitin gwaji (kayan aiki, sigogi, bayanan ma'auni) ana iya maimaita su?
Gabaɗaya: Shin za a iya amfani da dabarun gine-gine na tsakiya (layin aiki, vectorization) zuwa wasu algorithms (misali, AES, SHA-3)?

Misalin Hali: Yin Amfani da Tsarin

Bari mu yi amfani da ma'ana #5 (Gabaɗaya) ga algorithm ɗin AES. Dabarar takardar tana da canzawa sosai:

Tsarin Aiki Tare da Layi: AES-128 yana da zagaye 10. Za a iya gina layin aiki mai matakai 10 (ko mai zurfi ta hanyar buɗewa).
Ingantaccen Watsa Bayanai: Ingantaccen faɗi da tsarin bayanai ɗaya zai shafi ciyar da kernel ɗin AES.
Vectorization na Kernel: Ayyukan AES akan matrix ɗin yanayin bit 128 suna da iyawar aiki tare sosai a cikin toshe guda ɗaya.
Kwafin Naúrar Lissafi: Za a iya ƙirƙirar cibiyoyin AES masu zaman kansu da yawa.

Babban canjin gine-gine zai maye gurbin hanyar bayanai ta aikin $F$ na DES da canjin zagaye na AES (SubBytes, ShiftRows, MixColumns, AddRoundKey). Ka'idojin ingantawa sun kasance iri ɗaya. Wani bincike mai kama da wannan daga masu bincike a ETH Zurich akan haɓakar AES na tushen OpenCL akan FPGAs ya sami nasarori masu kama da wannan, yana tabbatar da gabaɗayan wannan hanyar.

8. Ayyukan Gaba & Hanyoyin Bincike

Nasarar wannan ƙirar ta buɗe hanyoyi masu ban sha'awa da yawa:

ɓoyayyen bayanai Bayan-Quantum (PQC): Ana ci gaba da daidaita algorithms na PQC (misali, ta NIST). Algorithms kamar CRYSTALS-Kyber (ɓoyayyar maɓalli) da CRYSTALS-Dilithium (sa hannu) sun haɗa da lissafin polynomial mai rikitarwa wanda ke da iyawar aiki tare kuma yana da ƙarfin lissafi, yana mai da su manufa masu dacewa don wannan ƙirar haɓakar FPGA.
Haɓaka ɓoyayyen bayanai na Homomorphic: Yin lissafi akan bayanan da aka ɓoye yana da iyaka sosai. Ingantattun na'urorin haɓaka FPGA na iya sa wasu tsare-tsaren homomorphic su zama masu amfani ga amfani na ainihi.
Haɗaɗɗun Naúrar Sarrafa Bayanai masu Tsaro: Haɗa wannan na'urar haɓaka ɓoyayyen bayanai tare da masu sarrafa hanyar sadarwa (SmartNICs) ko masu sarrafa ajiya don samar da ɓoyewa/buɗewa na bayanai a layi, mara ganuwa, don bayanai-a-wuri da bayanai-a-motsi a cikin cibiyoyin bayanai.
Haɓaka Toolchain: Bincike na gaba zai iya mayar da hankali kan sarrafa dabarun ingantawa da aka gabatar a nan. Shin mai haɗa kai na OpenCL zai iya gano mafi kyawun faɗin bit na bayanai ko ba da shawarar kwafin naúrar lissafi bisa binciken kernel da albarkatun FPGA da aka yi niyya?
Na'urorin Haɓakawa Masu Sauƙi na Algorithm da yawa: Ƙirƙirar kernels masu iya sake tsarawa waɗanda za su iya tallafawa cipher ɗin siminti da yawa (3DES, AES, ChaCha20) dangane da buƙatar aiki, suna amfani da ikon sake tsarawa na ɓangare na FPGA na zamani.

9. Nassoshi

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Khronos Group. (2024). OpenCL Overview. https://www.khronos.org/opencl/
Intel Corporation. (2023). Intel FPGA SDK for OpenCL. https://www.intel.com/content/www/us/en/software/programmable/sdk-for-opencl/overview.html
Ismail, A., & Shannon, L. (2019). High-Level Synthesis for FPGA-Based Cryptography: A Survey. In Proceedings of the International Conference on Field-Programmable Technology (FPT).
University of Toronto, Department of Electrical & Computer Engineering. (2022). Research in High-Level Synthesis and FPGA Architectures. https://www.eecg.utoronto.ca/~jayar/research/hls.html
ETH Zurich, Secure & Reliable Systems Group. (2021). Hardware Acceleration of Modern Cryptography. https://srs.group.ethz.ch/research.html
Zhuo, L., & Prasanna, V. K. (2005). High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware. IEEE Transactions on Parallel and Distributed Systems.